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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a +5 volt, parallel input complete 12-bit dac dac8562 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram 12-bit dac dac register ref 12 12 data refout dgnd v out agnd v dd clr ce dac-8562 general description the dac8562 is a complete, parallel input, 12-bit, voltage out- put dac designed to operate from a single +5 volt supply. built using a cbcmos process, these monolithic dacs offer the user low cost, and ease-of-use in +5 volt only systems. included on the chip, in addition to the dac, is a rail-to-rail amplifier, latch and reference. the reference (refout) is trimmed to 2.5 volts, and the on-chip amplifier gains up the dac output to 4.095 volts full scale. the user needs only sup- ply a +5 volt supply. the dac8562 is coded straight binary. the op amp output swings from 0 to +4.095 volts for a one millivolt per bit resolu- tion, and is capable of driving 5 ma. built using low tempera- ture-coefficient silicon-chrome thin-film resistors, excellent linearity error over temperature has been achieved as shown be- low in the linearity error versus digital input code plot. digital interface is parallel and high speed to interface to the fastest processors without wait states. the interface is very sim- ple requiring only a single ce signal. an asynchronous clr in- put sets the output to zero scale. the dac8562 is available in two different 20-pin packages, plastic dip and sol-20. each part is fully specified for opera- tion over C40 c to +85 c, and the full +5 v 5% power supply range. for mil-std-883 applications, contact your local adi sales office for the dac8562/883 data sheet which specifies opera- tion over the C55 c to +125 c temperature range. 1 ? 4096 ?.5 ?.75 0 0 ?.25 0.25 0.5 0.75 3072 2048 1024 v dd = +5v t a = ?5 c, +25 c, +125 c linearity error ?lsb digital input code ?decimal ?5 c +25 c & +125 c figure 1. linearity error vs. digital input code plot features complete 12-bit dac no external components single +5 volt operation 1 mv/bit with 4.095 v full scale true voltage output, 6 5 ma drive very low power C3 mw applications digitally controlled calibration servo controls process control equipment pc peripherals
dac8562Cspecifications electrical characteristics parameter symbol condition min typ max units static performance resolution n note 2 12 bits relative accuracy inl e grade C1/2 1/4 +1/2 lsb f grade C1 3/4 +1 lsb differential nonlinearity dnl no missing codes C1 3/4 +1 lsb zero-scale error v zse data = 000 h +1/2 +3 lsb full-scale voltage v fs data - fff h 3 e grade 4.087 4.095 4.103 v f grade 4.079 4.095 4.111 v full-scale tempco tcv fs notes 3, 4 16 ppm/ c analog output output current i out data = 800 h 5 7ma load regulation at half scale ld reg r l = 402 w to , data = 800 h 1 3 lsb capacitive load c l no oscillation 4 500 pf reference output output voltage v ref 2.484 2.500 2.516 v output source current i ref note 5 5 7 ma line rejection ln rej 0.08 %/v load regulation ld reg i ref = 0 to 5 ma 0.1 %/ma logic inputs logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i il 10 m a input capacitance c il note 4 10 pf interface timing specifications 1, 4 chip enable pulse width t cew 30 ns data setup t ds 30 ns data hold t dh 10 ns clear pulse width t clrw 20 ns ac characteristics 4 voltage output settling time 6 t s to 1 lsb of final value 16 m s digital feedthrough 35 nv sec supply characteristics positive supply current i dd v ih = 2.4 v, v il = 0.8 v 3 6 ma v il = 0 v, v dd = +5 v 0.6 1 ma power dissipation p diss v ih = 2.4 v, v il = 0.8 v 15 30 mw v il = 0 v, v dd = +5v 3 5 mw power supply sensitivity pss d v dd = 5% 0.002 0.004 %/% notes 1 all input control signals are specified with t r = t f = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 2 1 lsb = 1 mv for 0 to +4.095 v output range. 3 includes internal voltage reference error. 4 these parameters are guaranteed by design and not subject to production testing. 5 very little sink current is available at the refout pin. use external buffer if setting up a virtual ground. 6 the settling time specification does not apply for negative going transitions within the last 6 lsbs of ground. some devices exhibit double the typical settling time in this 6 lsb region. specifications subject to change without notice. C2C (@ v dd = +5.0 6 5%, r s = no load, C40 8 c t a +85 8 c, unless otherwise noted) rev. a
wafer test limits parameter symbol condition min typ max units static performance relative accuracy inl C1 3/4 +1 lsb differential nonlinearity dnl no missing codes C1 3/4 + 1 lsb zero-scale error v zse data = 000 h +1/2 +3 lsb full-scale voltage v fs data = fff h 4.085 4.095 4.105 v reference output voltage v ref 2.490 2.500 2.510 v logic inputs logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i il 10 m a supply characteristics positive supply current i dd v ih = 2.4 v, v il = 0.8 v 3 6 ma v il = 0 v, v dd = +5 v 0.6 1 ma power dissipation p diss v ih = 2.4 v, v il = 0.8 v 15 30 mw v il = 0 v, v dd = +5 v 35mw power supply sensitivity pss d v dd = 5% 0.002 0.004 %/% note 1 electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. caution esd (electrostatic discharge) sensitive device. the digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. unused devices must be stored in conductive foam or shunts. the protective foam should be discharged to the destination socket before devices are inserted. warning! esd sensitive device absolute maximum ratings* v dd to dgnd and agnd . . . . . . . . . . . . . . . . C0.3 v, +10 v logic inputs to dgnd . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v v out to agnd . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v v refout to agnd . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd i out short circuit to gnd . . . . . . . . . . . . . . . . . . . . . . 50 ma package power dissipation . . . . . . . . . . . . . . (t j max C t a )/ u ja thermal resistance u ja 20-pin plastic dip package (p) . . . . . . . . . . . . . . . . 74 c/w 20-lead soic package (s) . . . . . . . . . . . . . . . . . . . 89 c/w maximum junction temperature (t j max) . . . . . . . . . . 150 c operating temperature range . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 0 0 0 1 1 fs zs db 11? v out t cew t ds t dh data valid t clrw t s t s ? lsb error band ce clr figure 2. timing diagram table i. control logic truth table ce clr dac register function h h latched l h transparent - + h latched with new data x l loaded with all zeros h - + latched all zeros - + positive logic transition; x don't care. rev. a C3C (@ v dd = +5.0 v 6 5%, r l = no load, t a = +25 8 c, applies to part number dac8562gbc only, unless otherwise noted) dac8562
dac8562 rev. a C4C table ii. nominal output voltage vs. input code binary hex decimal output (v) 0000 0000 0000 000 0 0.000 zero scale 0000 0000 0001 001 1 0.001 0000 0000 0010 002 2 0.002 0000 0000 1111 00f 15 0.015 0000 0001 0000 010 16 0.016 0000 1111 1111 0ff 255 0.255 0001 0000 0000 100 256 0.256 0001 1111 1111 1ff 511 0.511 0010 0000 0000 200 512 0.512 0011 1111 1111 3ff 1023 1.023 0100 0000 0000 400 1024 1.024 0111 1111 1111 7ff 2047 2.047 1000 0000 0000 800 2048 2.048 half scale 1100 0000 0000 c00 3072 3.072 1111 1111 1111 fff 4095 4.095 full scale pin descriptions pin name description 20 v dd positive supply. nominal value +5 volts, 5%. 1-9 db0-db11 twelve binary data bit inputs. db11 17-19 is the msb and db0 is the lsb. 16 ce chip enable. active low input. 15 clr active low digital input that clears the dac register to zero, setting the dac to minimum scale. 8 dgnd digital ground for input logic. 12 agnd analog ground. ground reference for the internal bandgap reference voltage, the dac, and the output buffer. 13 v out voltage output from the dac. fixed output voltage range of 0 v to 4.095 v with 1 mv/lsb. an internal tempera- ture stabilized reference maintains a fixed full-scale voltage independent of time, temperature and power supply variations. 14 refout nominal 2.5 v reference output volt- age. this node must be buffered if re- quired to drive external loads. 11 nc no connection. leave pin floating. pin configurations 20-pin p-dip (n-20) sol-20 (r-20) ordering guide inl temperature package model (lsb) range option DAC8562EP 1/2 C40 c to +85 c n-20 dac8562fp 1 C40 c to +85 c n-20 dac8562fs 1 C40 c to +85 c r-20 dac8562gbc 1 +25 c dice dice characteristics 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 dgnd agnd v out refout clr ce db0 db1 db2 v dd db11 db10 db9 db6 db5 db4 db3 db8 db7 substrate is common with v dd . transistor count: 524 die size: 0.70 x 0.105 inch; 7350 sq mils 1 top view (not to scale) dac-8562 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 top view (not to scale) dac-8562 db3 db4 db5 db6 db7 db8 db9 db10 db11 dgnd v dd db2 db1 db0 refout v out agnd nc nc = no connect ce clr
dac8562 rev. a C5C operation the dac8562 is a complete ready to use 12-bit digital-to- analog converter. only one +5 v power supply is necessary for operation. it contains a voltage-switched, 12-bit, laser-trimmed digital-to-analog converter, a curvature-corrected bandgap refer- ence, a rail-to-rail output op amp, and a dac register. the par- allel data interface consists of 12 data bits, db0Cdb11, and a active low ce strobe. in addition, an asynchronous clr pin will set all dac register bits to zero causing the v out to be- come zero volts. this function is useful for power on reset or system failure recovery to a known state. d/a converter section the internal dac is a 12-bit voltage-mode device with an out- put that swings from agnd potential to the 2.5 volt internal bandgap voltage. it uses a laser trimmed r-2r ladder which is switched by n channel mosfets. the output voltage of the dac has a constant resistance independent of digital input code. the dac output (not available to the user) is internally connected to the rail-to-rail output op amp. amplifier section the internal dacs output is buffered by a low power con- sumption precision amplifier. this low power amplifier contains a differential pnp pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zero- scale dac output voltages. the rail-to-rail amplifier is config- ured in a gain of 1.6384 (= 4.095 v/2.5 v) in order to set the 4.095 volt full-scale output (1 mv/lsb). see figure 3 for an equivalent circuit schematic of the analog section. r1 r2 v out rail-to-rail output amplifier r bandgap reference refout 2.5v 2r r 2r 2r 2r spdt n ch fet switches 2r av = 4.096/2.5 = 1.636v/v voltage switched 12-bit r-2r d/a converter buffer figure 3. equivalent dac8562 schematic of analog portion the op amp has a 16 m s typical settling time to 0.01%. there are slight differences in settling time for negative slewing signals versus positive. see the oscilloscope photos in the typical per- formances section of this data sheet. output section the rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its n channel pull down fets that will pull an output load directly to gnd. the output sourcing current is provided by a p channel pull-up device that can sup- ply gnd terminated loads, especially important at the C5% supply tolerance value of 4.75 volts. v dd v out agnd n-ch p-ch figure 4. equivalent analog output circuit figures 5 and 6 in the typical performance characteristics sec- tion provide information on output swing performance near ground and full scale as a function of load. in addition to resis- tive load driving capability, the amplifier has also been carefully designed and characterized for up to 500 pf capacitive load driving capability. reference section the internal 2.5 v curvature-corrected bandgap voltage refer- ence is laser trimmed for both initial accuracy and low tempera- ture coefficient. the voltage generated by the reference is available at the refout pin. since refout is not intended to drive external loads, it must be bufferedCrefer to the applica- tions section for more information. the equivalent emitter fol- lower output circuit of the refout pin is shown in figure 3. bypassing the refout pin is not required for proper opera- tion. figure 7 shows broadband noise performance. power supply the very low power consumption of the dac8562 is a direct result of a circuit design optimizing use of the cbcmos pro- cess. by using the low power characteristics of the cmos for the logic, and the low noise, tight matching of the complemen- tary bipolar transistors, good analog accuracy is achieved. for power-consumption sensitive applications it is important to note that the internal power consumption of the dac8562 is strongly dependent on the actual logic-input voltage-levels present on the db0Cdb11, ce and clr pins. since these in- puts are standard cmos logic structures, they contribute static power dissipation dependent on the actual driving logic v oh and v ol voltage levels. the graph in figure 9 shows the effect on to- tal dac8562 supply current as a function of the actual value of input logic voltage. consequently for optimum dissipation use of cmos logic versus ttl provides minimal dissipation in the static state. a v inl = 0 v on the db0Cdb11 pins provides the lowest standby dissipation of 600 m a with a +5 v power supply.
dac8562 rev. a C6C as with any analog system, it is recommended that the dac8562 power supply be bypassed on the same pc card that contains the chip. figure 10 shows the power supply rejection versus frequency performance. this should be taken into ac- count when using higher frequency switched-mode power sup- plies with ripple frequencies of 100 khz and higher. one advantage of the rail-to-rail output amplifier used in the dac8562 is the wide range of usable supply voltage. the part is fully specified and tested over temperature for operation from +4.75 v to +5.25 v. if reduced linearity and source current ca- pability near full scale can be tolerated, operation of the dac8562 is possible down to +4.3 volts. the minimum operat- ing supply voltage versus load current plot, in figure 11, pro- vides information for operation below v dd = +4.75 v. timing and control the dac8562 has a 12-bit dac register that simplifies inter- face to a 12-bit (or wider) data bus. the latch is controlled by the chip enable ( ce ) input. if the application does not involve a data bus, wiring ce low allows direct operation of the dac. the data latch is level triggered and acquires data from the data bus during the time period when ce is low. when ce goes high, the data is latched into the register and held until ce re- turns low. the minimum time required for the data to be present on the bus before ce returns high is called the data setup time (t ds ) as seen in figure 2. the data hold time (t dh ) is the amount of time that the data has to remain on the bus after ce goes high. the high speed timing offered by the dac8562 provides for direct interface with no wait states in all but the fastest microprocessors. typical performance characteristics 5 2 0 10 100 100k 10k 1k 1 3 4 load resistance ? w output voltage ?volts rl tied to agnd d = fffh r l tied to agnd data = fffh v dd = +5v t a = +25 c r l tied to +5v data = 000h figure 5. output swing vs. load time = 1ms/div 10 90 100 0% 50mv 1ms t a = 25? nbw = 630khz output noise voltage ?500?/div figure 8. broadband noise 1 10 1000 100 100 1 0.01 0.1 10 output sink current ?? output pulldown voltage ?mv v dd = +5v data = 000h t a = +85 c t a = ?0 c t a = +25 c figure 6. pull-down voltage vs. output sink current capability 5 0 5 1 0 3 2 4 3 24 1 logic voltage value ?volts supply current ?ma v dd = +5v t a = +25 c figure 9. supply current vs. logic input voltage 80 ?00 ?0 ?0 1 ?0 ?0 0 20 40 60 3 2 output voltage ?volts output current ?ma pos 0 current 0 limit 0 neg current limit data = 800h r l tied to +2v figure 7. i out vs. v out 100 0 10 100 100k 10k 1k 60 80 20 40 power supply rejection ?db frequency ?hz v dd = +5v ?00mv ac t a = +25 c data = fffh figure 10. power supply rejection vs. frequency
dac8562 rev. a C7C 0.01 0.1 10 1.0 5.0 4.8 4.0 4.6 4.4 4.2 0.04 0.4 4.0 output load current ?ma v dd min ?volts d vfs 1 lsb data = fffh t a = +25 c proper operation when v dd supply voltage above curve figure 11. minimum supply voltage vs. load 0 5 16? v dd = +5v t a = +25 c output voltage 1mv/div data time ?10?/div figure 14. output voltage rise time detail 50 0 10 30 20 40 ? ? 16 10 12 68 14 4 0 ? ? 2 total unadjusted error ?lsb number of units tue = inl+zs+fs ss = 300 units t a = +25 c s figure 17. total unadjusted error histogram 2.028 2.018 2.048 2.038 0 5 time ?200ns/div v out ?volts ce data = 2048 10 to 2047 10 figure 12. midscale transition performance 0 5 v dd = +5v t a = +25 c output voltage 1mv/div data time ?10?/div 16? figure 15. output voltage fall time detail 4.125 4.115 4.105 4.095 4.085 4.075 ?0 ?5 0 25 50 75 100 125 avg +1 s avg avg ? s v dd = +5v no load ss = 300 pcs temperature ? c full-scale output ?olts figure 18. full-scale voltage vs. temperature 5 0 4 3 2 1 0 10 90 100 0% time = 20?/div 20? 1v input output 5v v dd = +5v t a = +25 c figure 13. large signal settling time +25 c & +85 c v dd = +5v t a = ?0 c, 25 c, +85 c ?0 c 2.0 1.5 1.0 0.5 0.0 ?.5 ?.0 ?.5 ?.0 0 1024 1536 2048 2560 3072 3584 4096 512 digital input code ?decimal linearity error ?lsb figure 16. linearity error vs. digital code 3 ? 125 0 ?5 ?0 1 2 100 75 50 25 0 temperature ? c zero-scale ?mv data = 000h no load v dd = +5.0v figure 19. zero-scale voltage vs. temperature
dac8562 rev. a C8C 10 0.1 0.01 10 100 100k 10k 1k 1 frequency ?hz v dd = +5v t a = 25 c data = fff h output noise density ??/ hz figure 20. output voltage noise density vs. frequency 0v 0v time = 1?/div 10 90 100 0% 2v 1? 2v v dd v ref t a = +25 c r l = figure 23. reference startup vs. time 8 0 125 2 1 ?5 ?0 4 3 5 6 7 100 75 50 25 0 temperature ? c supply current ?ma vdata = +2.4v no load v dd = +4.75v v dd = +5.25v v dd = +5.0v figure 22. supply current vs. temperature 10 8 6 4 2 0 ? ? ? ? ?0 ?0 ?5 0 25 50 75 100 125 avg +1 s avg ? s x v dd = +5v sample size = 300 temperature ? c v ref out error ?v figure 25. reference error vs. temperature 5 ? 1200 ? ? 200 ? 0 1 ? 0 2 3 4 1000 600 800 400 output voltage change ?mv hours of operation at +125? 135 units tested readings normalized to zero hour time point avg range v dd = +5v data = fff h figure 21. long-term drift accelerated by burn-in 1 0 10 90 100 0% time = 20?/div 5? 5v data v out 5mv/div a4 0.040 v dly 13.82 ? 5mv b l w ce = high figure 24. digital feedthrough vs. time 0.10 0.00 125 ?5 0.02 ?0 0.06 0.04 0.08 100 50 75 0 25 temperature ? c ref line regulation ?%/volt avg v dd = +4.75 to +5.25v sample size = 302 pcs avg ?3 s avg + 3 s figure 27. reference line regulation vs. temperature 0.005 0.000 125 ?5 0.001 ?0 0.003 0.002 0.004 100 50 75 0 25 temperature c ref load regulation ?%/ma avg v dd = +5v il = 5ma sample size = 302 pcs avg ?3 s d avg + 3 s figure 26. reference load regulation vs. temperature dac8562 Ctypical performance characteristics
dac8562 rev. a C9C applications section power supplies, bypassing, and grounding all precision converter products require careful application of good grounding practices to maintain full-rated performance. because the dac8562 has been designed for +5 v applications, it is ideal for those applications under microprocessor or micro- computer control. in these applications, digital noise is preva- lent; therefore, special care must be taken to assure that its inherent precision is maintained. this means that particularly good engineering judgment should be exercised when address- ing the power supply, grounding, and bypassing issues using the dac8562. the power supply used for the dac8562 should be well filtered and regulated. the device has been completely characterized for a +5 v supply with a tolerance of 5%. since a +5 v logic sup- ply is almost universally available, it is not recommended to connect the dac directly to an unfiltered logic supply without careful filtering. because it is convenient, a designer might be inclined to tap a logic circuit s supply for the dacs supply. unfortunately, this is not wise because fast logic with nanosec- ond transition edges induces high current pulses. the high tran- sient current pulses can generate glitches hundreds of millivolts in amplitude due to wiring resistances and inductances. this high frequency noise will corrupt the analog circuits internal to the dac and cause errors. even though their spike noise is lower in amplitude, directly tapping the output of a +5 v system supplies can cause errors because these supplies are of the switching regulator type that can and do generate a great deal of high frequency noise. therefore, the dac and any associated analog circuitry should be powered directly from the system power supply outputs using appropriate filtering. figure 28 illustrates how a clean, analog-grade supply can be generated from a +5 v logic supply using a differential lc filter with sepa- rate power supply and return lines. with the values shown, this filter can easily handle 100 ma of load current without saturat- ing the ferrite cores. higher current capacity can be achieved with larger ferrite cores. for lowest noise, all electrolytic capaci- tors should be low esr (equivalent series resistance) type. 100? elect. 10-22? tant. 0.1? cer. ttl/cmos logic circuits +5v power supply +5v +5v return ferrite beads: 2 turns, fair-rite #2677006301 figure 28. properly filtering a +5 v logic supply can yield a high quality analog supply the dac8562 includes two ground connections in order to minimize system accuracy degradation arising from grounding errors. the two ground pins are designated dgnd (pin 10) and agnd (pin 12). the dgnd pin is the return for the digi- tal circuit sections of the dac and serves as their input thresh- old reference point. thus dgnd should be connected to the same ground as the circuitry that drives the digital inputs. pin 12, agnd, serves as the supply rail for the internal voltage reference and the output amplifier. this pin should also serve as the reference point for all analog circuitry associated with the dac8562. therefore, to minimize any errors, it is recom- mended that the agnd connection of the dac8562 be con- nected to a high quality analog ground. if the system contains any analog signal path carrying a significant amount of current, then that path should have its own return connection to pin 12. it is often advisable to maintain separate analog and digital grounds throughout a complete system, tying them common to one place only. if the common tie point is remote and an acci- dental disconnection of that one common tie point were to occur due to card removal with power on, a large differential voltage between the two commons could develop. to protect devices that interface to both digital and analog parts of the sys- tem, such as the dac8562, it is recommended that the com- mon ground tie points be provided at each such device. if only one system ground can be connected directly to the dac8562, it recommended that the analog common be used. if the systems agnd has suitably low impedance, then the digital signal currents flowing in it should not seriously affect the ground noise. the amount of digital noise introduced by con- necting the two grounds together at the device will not adversely affect system performance due to loss of digital noise immunity. generous bypassing of the dacs supply goes a long way in re- ducing supply line-induced errors. local supply bypassing con- sisting of a 10 m f tantalum electrolytic in parallel with a 0.1 m f ceramic is recommended. the decoupling capacitors should be connected between the dacs supply pin (pin 20) and the ana- log ground (pin 12). figure 29 shows how the dgnd, agnd, and bypass connections should be made to the dac8562. 15 16 dgnd agnd v dd data 13 dac-8562 12 10? 0.1? v out to other analog circuits 20 +5v 10 to power ground ce clr figure 29. recommended grounding and bypassing scheme for the dac-8562
dac8562 rev. a C10C 15 16 dgnd agnd data dac-8562 13 v out +12v or +15v 10 ce clr 1 12 0.1? 4 ref-02 6 2 0.1? figure 31. operating the dac8562 on +12 v or +15 v supplies using a ref02 voltage reference measuring offset error one of the most commonly specified endpoint errors associated with real-world nonideal dacs is offset error. in most dac testing, the offset error is measured by applying the zero-scale code and measuring the output deviation from 0 volt. there are some dacs where offset errors may be present but not observable at the zero scale because of other circuit limi- tations (for example, zero coinciding with single supply ground). in these dacs, nonzero output at zero code cannot be read as the offset error. in the dac8562, for example, the zero-scale er- ror is specified to be +3 lsbs. since zero scale coincides with zero volt, it is not possible to measure negative offset error. by adding a pull-down resistor from the output of the dac8562 to a negative supply as shown in figure 32, offset er- rors can now be read at zero code. this configuration forces the output p-channel mosfet to source current to the negative supply thereby allowing the designer to determine in which di- rection the offset error appears. the value of the resistor should be such that, at zero code, current through the resistor is 200 m a maximum. 15 16 dgnd agnd v dd data dac-8562 13 0.1? v out +5v 10 ce clr 20 12 200? max v figure 32. measuring zero-scale or offset error unipolar output operation this is the basic mode of operation for the dac8562. as shown in figure 30, the dac8562 has been designed to drive loads as low as 820 w in parallel with 500 pf. the code table for this op- eration is shown in table iii. 15 16 dgnd agnd v dd data dac-8562 13 10? 0.1? 0v v out 4.095v +5v 10 ce clr 20 12 820 500pf w figure 30. unipolar output operation table iii. unipolar code table hexadecimal number decimal number analog output in dac register in dac register voltage (v) fff 4095 +4.095 801 2049 +2.049 800 2048 +2.048 7ff 2047 +2.047 000 0 0 operating the dac8562 on +12 v or +15 v supplies only although the dac8562 has been specified to operate on a single, +5 v supply, a single +5 v supply may not be available in many applications. since the dac8562 consumes no more than 6 ma, maximum, then an integrated voltage reference, such as the ref02, can be used as the dac8562 +5 v supply. the configuration of the circuit is shown in figure 31. notice that the references output voltage requires no trimming because of the ref02s excellent load regulation and tight initial output voltage tolerance. although the maximum supply current of the dac8562 is 6 ma, local bypassing of the ref02s output with at least 0. 1 m f at the dacs voltage supply pin is recommended to prevent the dacs internal digital circuits from affecting the dacs internal voltage reference.
dac8562 rev. a C11C 15 16 dgnd agnd v dd data dac-8562 13 10? 0.1? ?v v o +5v +5v 10 ce clr 20 12 14 refout v out r1 10k r2 12.7k ?.5v 2 3 4 8 a1 +5v ?v 1 p2 500 full scale adjust r4 23.7k p1 10k zero scale adjust r3 247k r5 10k r6 10k 6 5 a2 7 a1, a2 = 1/2 op-295 w w w w w w w figure 33. bipolar output operation bipolar output operation although the dac8562 has been designed for single supply op- eration, bipolar operation is achievable using the circuit illus- trated in figure 33. the circuit uses a single supply, rail-to-rail op295 op amp and the dacs internal +2.5 v reference to gen- erate the C2.5 v reference required to level-shift the dac out- put voltage. the circuit has been configured to provide an output voltage in the range C5 v v out +5 v and is coded in complementary offset binary. although each dac lsb corre- sponds to 1 mv, each output lsb has been scaled to 2.44 mv. table iv provides the relationship between the digital codes and output voltage. the transfer function of the circuit is given by: v o =- 1 mv digital code r 4 r 1 ? ? ? ? + 2.5 r 4 r 2 ? ? ? ? and, for the circuit values shown, becomes: v o = 2.44 mv digital code + 5 v table iv. bipolar code table hexadecimal number decimal number analog output in dac register in dac register voltage (v) fff 4095 C4 9976 801 2049 C2.44eC3 800 2048 0 7ff 2047 +2.44eC3 000 0 +5 to maintain monotonicity and accuracy, r1, r2, r4, r5, and r6 should be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coef- ficient matching. mismatching between r1 and r2 causes offset and gain errors while an r4 to r1 and r2 mismatch yields gain errors. for applications that do not require high accuracy, the circuit il- lustrated in figure 34 can also be used to generate a bipolar output voltage. in this circuit, only one op amp is used and no potentiometers are used for offset and gain trim the output voltage is coded in offset binary and is given by: v o = 1 mv digital code r 4 r 3 + r 4 ? ? ? ? 1 + r 2 r 1 ? ? ? ? refout r 2 r 1 ? ? ? ? for the 2 5 v output range and the circuit values shown in the table, the transfer equation becomes: v o = 1. 2 2 mv digital code 2.5 v similarly, for the 5 v output range, the transfer equation be- comes: v o = 2. 44 mv digital code 5 v note that, for 5 v output voltage operation, r5 is required as a pull-down for refout. or, refout can be buffered by an op amp configured as a follower that can source and sink cur- rent. 15 16 data dac-8562 13 ce clr dgnd agnd 10 12 v dd 0.1? +5v 20 14 refout v out r1 r5 4.99k a1 = 1/2 op-295 r4 r3 r2 2 3 4 8 a1 +5v ?v 1 v o v out range ?.5v ?v r1 10k 10k r2 10k 20k r3 10k 10k r4 15.4k + 274 43.2k + 499 w figure 34. bipolar output operation without trim version 1
dac8562 rev. a C12C alternatively, the output voltage can be coded in complementary offset binary using the circuit in figure 35. this configuration eliminates the need for a pull-down resistor or an op amp for refout the transfer equation of the circuit is given by: v o = 1 mv digital code r 2 r 1 ? ? ? ? + refout r 4 r 3 + r 4 ? ? ? ? 1 + r 2 r 1 ? ? ? ? and, for the values shown, becomes: v o =- 2. 44 mv digital code + 5 v dac-8562 refout v out r1 r4 r3 r2 v o v o range ?v r2 23.7k + 715 r4 13.7k + 169 r1 = r3 = 10k w w figure 35 bipolar output operation without trim version 2 generating a negative supply voltage some applications may require bipolar output configuration, but only have a single power supply rail available. this is very com- mon in data acquisition systems using microprocessor-based sys- tems. in these systems, only +12 v, +15 v, and/or +5 v are available. shown in figure 36 is a method of generating a nega- tive supply voltage using one cd4049, a cmos hex inverter, operating on +12 v or +15 v. the circuit is essentially a charge pump where two of the six are used as an oscillator. for the val- ues shown, the frequency of oscillation is approximately 3.5 khz and is fairly insensitive to supply voltage because r1 > 2 3 r2. the remaining four inverters are wired in parallel for higher out- put current. the square-wave output is level translated by c2 to a negative-going signal, rectified using a pair of 1n4001s, and then filtered by c3. with the values shown, the charge pump will provide an output voltage of C5 v for current loading in the range 0.5 ma i out 10 ma with a +15 v supply and 0.5 ma i out 7 ma with a +12 v supply. 910 6 11 12 14 15 7 3254 r2 5.1k r1 510k c1 0.02? c2 47? d1 1n4001 c3 47? 1n5231 5.1v zener d2 1n4001 r3 470 ?v inverters = cd4049 w w w figure 36. generating a C5 v supply when only +12 v or +15 v are available audio volume control the dac8562 is well suited to control digitally the gain or attenuation of a voltage controlled amplifiers. in professional audio mixing consoles, music synthesizers, and other audio proces- sors, vcas, such as the ssm2018, adjust audio channel gain and attenuation from front panel potentiometers. the vca provides a clean gain transition control of the audio level when the slew rate of the analog input control voltage, v c , is properly chosen. the cir- cuit in figure 37 illustrates a volume control application using the dac8562 to control the attenuation of the s sm2018. 15 16 dgnd agnd data dac-8562 13 +15v 10 ce clr 20 12 0.1? 4 ref-02 6 2 0.1? 18k 10pf 470k p1 100k w 10m offset trim 47pf symmetry trim p2 500k w v out +15v ?5v 30k +15v ?5v 0.1? 0.1? +15v 18k v in 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssm-2018 +5v c con 1? r6 825 r7 1k w * 0v v c +2.24v * ?precision resistor pt146 1k w compensator w w w w w w figure 37. audio volume control since the supply voltage available in these systems is typically 15 v or 18 v, a ref02 is used to supply the +5 v required to power the dac. no trimming of the reference is required be- cause of the references tight initial tolerance and low supply current consumption of the dac8562. the ssm2018 is config- ured as a unity-gain buffer when its control voltage equals 0 volt. this corresponds to a 000 h code from the dac8562. since the ssm2018 exhibits a gain constant of C28 mv/db (typical), the dacs full-scale output voltage has to be scaled down by r6 and r7 to provide 80 db of attenuation when the digital code equals fff h . therefore, every dac lsb corre- sponds to 0.02 db of attenuation. table v illustrates the attenu- ation versus digital code of the volume control circuit. table v. ssm2018 vca attenuation vs. dac8562 input code hexadecimal number control voltage vca attenuation in dac register (v) (db) 000 0 0 400 +0.56 20 800 +1.12 40 c00 +1.68 60 fff +2.24 80
dac8562 rev. a C13C to compensate for the ssm2018s gain constant temperature coefficient of C3300 ppm/ c, a 1 k w , temperature-sensitive resistor (r7) manufactured by the precision resistor com- pany with a temperature coefficient of +3500 ppm/ c is used. a c con of 1 m f provides a control transition time of 1 ms which yields a click-free change in the audio channel attenuation. sym- metry and offset trimming details of the vca can be found in the ssm2018 data sheet. information regarding the pt146 1 k w compensator can be obtained by contacting: precision resistor company, incorporated 10601 75th street north largo, fl 34647 (813) 541-5771 a high-compliance, digitally controlled precision current source the circuit in figure 38 shows the dac8562 controlling a high-compliance, precision current source using an amp05 in- strumentation amplifier. the amp05s reference pin becomes the input, and the old inputs now monitor the voltage across a precision current sense resistor, r cs . voltage gain is set to unity, so the transfer function is given by the following equation: i out = v in r cs if r cs equals 100 w , the output current is limited to +10 ma with a 1 v input. therefore, each dac lsb corresponds to 2.4 m a. if a bipolar output current is required, then the circuit in figure 33 can be modified to drive the amp05s reference pin with a 1 v input signal. potentiometer p1 trims the output current to zero with the in- put at 0 v. fine gain adjustment can be accomplished by adjust- ing r1 or r2. a digitally programmable window detector a digitally programmable, upper/lower limit detector using two dac8562s is shown in figure 39. the required upper and lower limits for the test are loaded into each dac individually by controlling hdac/ ldac . if a signal at the test input is not within the programmed limits, the output will indicate a logic zero which will turn the red led on. 9 18 1 2 17 r1 100k 7 6 r2 5k w p1 100k w 5 4 11 0.1? ?5v amp-05 10 r cs 100 w 0ma i out 10ma 2.4?/ lsb 12 0.1? +15v 15 dgnd agnd data dac-8562 13 +15v 10 16 ce clr 20 12 0.1? 4 ref-02 6 2 0.1? r3 3k r4 1k 8 figure 38. a high-compliance, digitally controlled precision current source 15 16 dgnd agnd dac-8562 13 10 12 0.1? 20 +5v 2 1 1/6 74hc05 hdac/ldac clr +5v 1k c1 c2 0.1? +5v 12 3 2 1 4 6 7 5 +5v r1 604 w red led t1 3 4 +5v r2 604 w green led t1 pass/fail c1, c2 = 1/4 cmp-404 15 16 dgnd agnd dac-8562 13 10 12 0.1? 20 +5v data 1/6 74hc05 v in w figure 39. a digitally programmable window detector
dac8562 rev. a C14C decoding multiple dac8562s the ce function of the dac8562 can be used in applications to decode a number of dacs. in this application, all dacs re- ceive the same input data; however, only one of the dacs ce input is asserted to transfer its parallel input register contents into the dac. in this circuit, shown in figure 40, the ce tim- ing is generated by a 74hc139 decoder and should follow the dac8562s standard timing requirements. to prevent timing errors, the 74hc139 should not be activated by its enable input while the coded address inputs are changing. a simple timing circuit, r1 and c1, connected to the dacs clr pins resets all dac outputs to zero during power-up. microprocessor interfacing dac-8562Cmc68hc11 interface the circuit illustrated in figure 41 shows a parallel interface be- tween the dac8562 and a popular 8-bit microcontroller, the m68hc11, which is configured in a single-chip operating mode. the interface circuit consists of a pair of 74act11373 transparent latches and an inverter. the data is loaded into the latches in two 8-bit bytes; the first byte contains the four most significant bits, and the lower 8 bits are in the second byte. data is taken from the microcontrollers port b output lines, and three interface control lines, clr , ce , and msb/ lsb , are con- trolled by the m68hc11's pc2, pc1, and pc0 output lines, re- spectively. to transfer data into the dac, pc0 is set, enabling u1s outputs. the first data byte is loaded into u1 where the four least significant bits of the byte are connected to msbCdb8. pc0 is then cleared; this latches u1s inputs and enables u2s outputs. u2s outputs now become db7Cdb0. the dac output is updated with the contents of u1 and u2 when pc1 is cleared. the dacs clr input, controlled by the m68hc11s pc2 output line, provides an asynchronous clear function that sets the dacs output to zero. included in this sec- tion is the source code for operating the dac-8562Cm68hc11 interface. v cc 1g 1a 1b 2g 2a 2b gnd 1y0 1y1 1y2 1y3 2y0 2y1 2y2 2y3 12 1k +5v 16 1 2 3 15 14 13 8 11 10 9 7 6 5 4 nc nc nc nc 0.1? +5v enable coded address +5v c1 0.1? r1 1k 15 dac-8562 #4 13 16 15 16 dac-8562 #1 13 15 dac-8562 #2 13 15 dac-8562 #3 13 16 16 v out1 v out3 v out4 v out2 data 74hc139 w w figure 40. decoding multiple dac8562s using the ce pin 13 23 22 21 20 1 16 15 14 24 1 2 3 4 9 10 11 12 u1 c 1d 2d 3d 4d 5d 6d 7d 8d oc 1q 2q 3q 4q 5q 6q 7q 8q 13 23 22 21 20 1 16 15 14 24 1 2 3 4 9 10 11 12 u2 c 1d 2d 3d 4d 5d 6d 7d 8d oc 1q 2q 3q 4q 5q 6q 7q 8q clr ce msb/ lsb 15 16 9 8 7 6 5 4 3 2 u3 clr ce msb db10 db9 db8 db7 db6 db5 db4 1 19 18 17 db3 db2 db1 lsb nc nc nc nc pc2 pc1 74act11373 *dac-8562 74act11373 v out 74hc04 *m6bhc11 pc2 pc1 pc0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 *additional pins omitted for clarity 1 2 13 figure 41. dac8562 to mc68hc11 interface
dac8562 rev. a C15C dac8562 C m68hc11 interface program source code * * dac8562 to m68hc11 interface assembly program * adolfo a. garcia * september 14, 1992 * * m68hc11 register definitions * portb equ $1004 portc equ $1003 port c control register * 0,0,0,0;0,clr/,ce/,msb-lsb/ ddrc equ $1007 port c data direction * * ram variables: msbs are encoded from 0 (hex) to f (hex) * lsbs are encoded from 00 (hex) to f (hex) * dac requires two 8-bit loads * msbs equ $00 hi-byte: 0,0,0,0;msb,db10,db9,db8 lsbs equ $01 lo-byte: db7,db6,db5,db4;db3,db2, db1,db0 * * main program * org $c000 start of users ram in evb init lds #$cfff top of c page ram * * initialize port c outputs * ldaa #$07 0,0,0,0;0,1,1,1 staa ddrc clr/,ce/, and msb-lsb/ are now enabled as outputs ldaa #$06 0,0.0,0;0,1,1,0 * clr/-hi, ce/-hi, msb-lsb/-lo staa portc initialize port c outputs * * call update subroutine * bsr update xfer 2 8-bit words to dac8562 jmp $e000 restart buffalo * * subroutine update * update pshx save registers x, y, and a pshy psha * * enter contents of the hi-byte input register * ldaa #$0a 0,0,0,0;1,0,1,0 staa msbs msbs are set to 0a (hex) * * enter contents of lo-byte input register * ldaa #$aa 1,0,1,0;1,0,1,0 staa lsbs lsbs are set to aa (hex) * ldx #msbs stack pointer at 1st byte to send via port b ldy #$1000 stack pointer at on-chip registers * * clear dac output to zero * bclr portc,y $04 assert clr/ bset portc,y $04 de-assert clr/ * * loading input buffer latches * bset portc,y $01 set hi-byte register load tfrlp ldaa 0,x get a byte to transfer via port b staa portb write data to input register inx increment counter to next byte for transfer cpx #lsbs+1 are we done yet ? beq dump if yes, update dac output bclr portc,y $01 latch hi-byte register and set lo-byte register load bra tfrlp * dac8562Cm68hc11 interface program source code (continued) * update dac output with contents of input registers * dump bclr portc,y $02 assert ce/ bset portc,y $02 latch dac register * pula when done, restore registers x, y & a puly pulx rts ** return to main program **
dac8562 rev. a C16C outline dimensions dimensions shown in inches and (mm). c1713C24C10/92 printed in u.s.a. 20-pin plastic dip (p-suffix) pin 1 0.255 (6.477) 0.245 (6.223) 20 1 11 10 0.145 (3.683) min 0.021 (0.533) 0.015 (0.381) 0.065 (1.66) 0.045 (1.15) 0.135 (3.429) 0.125 (3.17) seating plane 1.07 (27.18) max 0.11 (2.79) 0.09 (2.28) 0.125 (3.175) min 0.32 (8.128) 0.30 (7.62) 0.011 (0.28) 0.009 (0.23) 15 0 lead no. 1 identified by dot or notch leads are solder or tin-plated kovar or alloy 42. 20-pin cerdip (r-suffix) lead no. 1 identified by dot or notch leads are solder or tin-plated kovar or alloy 42. pin 1 10 11 1 20 0.28 (7.11) 0.24 (6.1) 15 0 0.011 (0.28) 0.009 (0.23) 0.32 (8.128) 0.29 (7.366) seating plane 0.97 (24.64) 0.935 (23.75) 0.20 (5.0) 0.14 (3.56) 0.15 (3.8) 0.125 (3.18) 0.02 (0.5) 0.016 (0.14) 0.11 (2.79) 0.09 (2.28) 0.07 (1.78) 0.05 (1.27) 0.18 (4.57) 0.125 (3.18) 20-lead soic (s-suffix) 0.022 (0.56) 0.014 (0.36) 0.050 (1.27) bsc 0.107 (2.72) 0.089 (2.26) 0.512 (13.00) 0.496 (12.60) 0.011 (0.275) 0.005 (0.125) 0.034 (0.86) 0.018 (0.46) 0.015 (0.38) 0.007 (0.18) pin 1 0.419 (10.65) 0.404 (10.00) 0.299 (7.60) 0.291 (7.40) 1 20 11 10

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